NoC System Generator
Overview
The NoC system Generator is a design flow, which can generate highly configurable NoC-based MPSoC for FPGA instantiation. The design flow has been developed to enable rapid HW/SW co-design and design space exploration (DSE) through emulation on FPGA. The generated multiprocessor platform connects the processors using the Nostrum NoC architecture and design methodology. The platform implements the distributed memory model and processors communicate using the provided communication primitives written in the C language, which are automatically generated by the flow and customized to provide services for the particular generated system.
Design Flow
The flow starts from a set of C application files and an XML configuration file. Through the XML file the user selects the target technology, NoC topology, kind of router and interconnection scheme. The flow automatically creates the multi processor implementation on the selected target FPGA, generates drivers to provide the communication primitives, and places the provided C application software on the cores specified by the user.
Features
- Graphic User Interfacee
- Auto Generation of NoC HDL
- Xilinx and Intel/Altera Compatible
- Nostrum NoC
- Scalablility
- Reduced Development Time
The NoC system Generator is a design flow, which can generate highly configurable NoC-based MPSoC for FPGA instantiation. The design flow has been developed to enable rapid HW/SW co-design and design space exploration (DSE) through emulation on FPGA. The generated multiprocessor platform connects the processors using the Nostrum NoC architecture and design methodology. The platform implements the distributed memory model and processors communicate using the provided communication primitives written in the C language, which are automatically generated by the flow and customized to provide services for the particular generated system.
The flow starts from a set of C application files and an XML configuration file. Through the XML file the user selects the target technology, NoC topology, kind of router and interconnection scheme. The flow automatically creates the multi processor implementation on the selected target FPGA, generates drivers to provide the communication primitives, and places the provided C application software on the cores specified by the user.Features
- Graphic User Interfacee
- Auto Generation of NoC HDL
- Xilinx and Intel/Altera Compatible
- Nostrum NoC
- Scalablility
- Reduced Development Time
Installation
Clone NSG HDLs
The latest NSG HDLs and directory structure can be obtained from the NSG Github repository:
$ git clone git://github.com/Noctegra/NSG.gitDownloading NSG Tool
The NSG toolchain binaries can be found under Releases and should be downloaded and extracted to NSG/bin/windows/
Configuration
Make sure to have a European (German, Swedish, etc) date & time format set (Control Panel -> Region and Language)
Visual C++ Redistributable for Visual Studio 2015
https://www.microsoft.com/en-us/download/confirmation.aspx?id=48145
Environmental Path
Directory Structure
| Directory Name | Description |
|---|---|
| Bin/ | NSG Binaries including GUI |
| Boards/ | Boards/Platform Description Files |
| Documentation/ | NSG User Manual |
| Papers/ | List of Related Publications |
| VHDL/ | NSG HDL repo for NoC |
Tutorials
Simulink to NoC-Based MPSOC
Synchronous Ring on 2x2 NoC
The 4 processors platform is configured so in this way:
- Central: CPU_0_0, jtag_0_0, cpu_id 1, jtag_id 1
- Engines: CPU_2_0, jtag_2_0, cpu_id 3, jtag_id 4
- EIR: CPU_1_0, jtag_1_0, cpu_id 2, jtag_id 3
- EPinsensor: CPU_3_0, jtag_3_0, cpu_id 0, jtag_id 0
In the demo application, each processor receives one data, increase the data by 1, send the data to the following processor. One data takes 1 second to be sent to the following processor. So, for example, CPU_0_0 receives the value 0, and send the value 1 to CPU_1_0. After 1 second CPU_1_0 receives the value 1, and send the value 2 to CPU_2_0....
To test the demo application there are 2 ways:
use the Nios IDE or Nios EDS to create 4 projects, each project for each CPU. The projects should start from the "Hello World small" template, or have the exact same setting in the BSP. Copy the software files (.c, .h) for each cpu in the corresponding NIOS IDE/EDS project. Build the 4 projects. Download the .sof file on the board. "Run as hardware" the projects in the following order: CPU0, 1 , 2, 3. All projects must run at the same time, do not stop them. You should see some output on the Nios2 terminals of the Nios IDE.
Open 5 Nios2 Shells. 4 shells will be used to connect to the 4 processors, 1 shell to execute the commands. For each of the 4 shell run 1 of this commands:
$ nios2-terminal -i 1
$ nios2-terminal -i 3
$ nios2-terminal -i 4
$ nios2-terminal -i 0You are connected to the 4 processors through 4 terminals. Download the .sof file on the board. With the 5th shell download the provided .elf files (the compiled code) on each core using the following commands, in sequence:
$ nios2-download -g -i 1 <path_to_file>/Node_0_0.elf
$ nios2-download -g -i 2 <path_to_file>/Node_1_0.elf
$ nios2-download -g -i 3 <path_to_file>/Node_2_0.elf
$ nios2-download -g -i 0 <path_to_file>/Node_3_0.elf